Microprocessor - DMA 8257 Controller
DMA stands for Direct Memory Access. It is designed by Intel to transfer data at the fastest rate. It allows the device to transfer data directly to / from memory without any interference from the processor.
Using a DMA controller, the device asks the processor to keep its data, address and control bus, so that the device is free to transfer data directly to / from memory. DMA data transfer is only started after receiving the HLDA signal from the CPU.
How are DMA operations performed?
Here is the sequence of operations performed by a DMA -
- Initially, when a device needs to send data between the device and memory, the device should send a DMA request (DRQ) to the DMA controller.
- The DMA controller sends a request for miwaits (HRQ) at the processor and waits for the processor to assert the HLDA.
- Then the microprocessor tri-indicates all the data bus, ess addrbus and control bus. The CPU exits control of the bus and acknowledges the HOLD request via the HLDA signal.
- The CPU is now in the HOLD state and the DMA controller must handle the operations on the buses between the Processor, memory and I / O devices.
Features of the 8257
Here is a list of some of the main features of the 8257 -
- It has four channels which can be used on four I / O devices
- Each channel has 16 bit address and 14 bit counter.
- Each channel can transfer data up to 64KB.
- Each channel can be programmed independently.
- Each channel can perform read transfer, write transfer and verifier transfer operations.
- It generates a MARK signal to the device that 128 bytes have been transferred.
- It requires a single phase clock.
- Its frequency varies from 250Hz to 3MHz.
- It works in 2 modes, namely, Master mode and slave mode .
The following image shows the architecture of 8257 -
Deion of pins 8257
The following image shows the pin diagram of a DMA 8257 controller -
DRQ 0 −DRQ 3
These are the four individual channel DMA request inputs , which are used by devices to use DMA services. When fixed priority mode is selected, then DRQ 0 has the highest priority and DRQ 3 has the highest priority. lowest priorityamong them.
DACK o - DACK 3
These are the active-low DMA acknowledgment lines, which put update the requesting device on the status of its request by the CPU. These lines can also act as strobe lines for requesting devices.
D o - D 7
These are bidirectional data lines which are used to interface the system bus with the DMA controller internal data bus. In Slave mode, it brings the command words to 8257 and the status word to 8257. In master mode, these lines are used to send the upper byte of the address generated to the flip-flop. This address is further locked using the ADSTB signal.
This is an active-low bidirectional tri-state input line, which is used by the CPU to read the internal registers of 8257 in slave mode. In master mode, it is used forread data from devices during a memory write cycle.
This is a bidirectional tri-state active line, which is used to load the contents of the data bus into the 8-bit mode register or the upper / lower byte of a 16-bit DMA address register or terminal count register. In master mode, it is used to load data to device devices during the DMA memory read cycle.
This is a clock frequency signal which is required for the internal operation of the 8257.
This signal is used to RESET the DMA controller by disabling all DMA channels.
A o - A 3
These are the four least significant address lines. In slave mode, they act as an input, which selects one of the registers to read or write. In master mode, these are the four lines ofThe least significant memory address output generated by 8257.
This is an active-low chip select row. In slave mode, it allows read / write operations to / from 8257. In master mode, it disables read / write operations to / from 8257.
A 4 - A 7
These are the upper nibble of the lower byte address generated by DMA in master mode.
This is an active-high hrone input signal, which prepares the DMA by inserting wait states.
This signal is used to receive the call waiting signal from the output device. In slave mode, it is connected to a DRQ 8257 input line. In master mode, it is connected to the HOLD input of the CPU.
This is the hold acknowledgment signal which indicates to the DMA controller that the bus has been granted to the requesting device by the CPU when itis set to 1.
This is the low memory read signal, which is used to read data from addressed memory locations during read cycles DMA.
This is the active low tri-state signal that is used to write data to the addressed memory location during the DMA write operation.
This signal is used to convert the high byte of the memory address generated by the DMA controller into locks.
This signal is used to deactivate the address bus / data bus.
It stands for 'Terminal Count ', which indicates the current DMA cycle to the present devices.
The mark will be activated after every 128 cycles or whole multiples thereof from the beginning. It indicates that the current DMA cycle is the 128th cycle from the previous MARK output to the selected device.
This is the power signal which is necessary for the operation of the circuit.