# VLSI Design - MOS Inverter

The inverter is really the core of all digital designs. Once its operation and properties are clearly understood, the design of more complex structures such as NAND gates, adders, multipliers, and microprocessors is greatly simplified. The electrical behavior of these complex circuits can be almost completely derived by extrapolating the results obtained for inverters.

The analysis of inverters can be extended to explain the behavior of more complex gates such as NAND, NOR or XOR, which in turn form the building blocks of modules such as multipliers and processors . In this chapter, we focus on a single incarnation of the inverter gate, namely static CMOS inverter - or CMOS inverter, in short. It is certainly the most popular at the moment and deserves to benc our special attention.

## Principle of operation

The logical symbol and the truth table of the ideal inverter are shown in the figure below. Here, A is the input and B is the inverted output represented by their node voltages. Using positive logic, the Boolean value of logic 1 is represented by V _{ dd } and logic 0 is represented by 0. V _{ th } is the threshold voltage of the inverter, which is V _{ dd } / 2, where V _{ dd } is the voltage output.

The output is switched from 0 to V _{ dd } when the input is less than V _{ th }. Thus, for 0 in e the output is equal to logic input 0 and V _{ th}indd equals logic1 input for inverter.

The characteristics shown in the figure are ideal. The generalized circuit structure of an nMOS inverter is shown in the figure below.

From SS = 0. The output node is connected with a localized capacity used for VTC.

## Resistive load inverter

The basic structure of a resistive load inverter is shown in the figure below. Here the nMOS enhancement type acts like the pilot transistor. The load consists of a simple linear resistor R _{ L }. The circuit power supply is V _{ DD } and the drain current I _{ D } is equal to the load current I _{ R }.

### Circuit operation

When the input of the pilot transistor is less than the threshold voltage V _{ TH } (V _{ in } TH ), the pilot transistor is in the region of cut off and conduct no current. Thus, the voltage drop across the load resistor is zero and the output voltage is equal to V _{ DD }. Now when the input voltage increases further, the pilot transistor will start to conduct the non-zero current and nMOS will go into the saturation region.

Mathematically,

$$ I_ {D} = frac {K_ {n}} {2} left [V_ {GS} -V_ {TO} right] ^ {2} $$

By increasing the input voltage further, the transistor drives enter the linear region and the output of the pilot transistor decreases.

$$ I_ {D} = frac {K_ {n}} {2} 2 left [V_ {GS} -V_ {TO} right ] V_ {DS} -V_ {DS} ^ {2} $$

Reserve VTC The five-load inverter, shown below, indicates the operating mode of the pilot transistor and voltage points.

## Inverter with N-type MOSFET load

The main advantage of using MOSFET as a load device is that the silicon area occupied by the transistor is smaller than the area occupied by resistive load. Here MOSFET is active load and active load inverter gives better performance than resistive load inverter.

## Enhancement Load NMOS

Two inverters with enhancement type load device are shown in the figure. The load transistor can operate either, in the saturation region or in the linear region, depending on the bias voltage applied to its terminal grid The saturated enhancement load inverter is shown in fig. (a). It requires a single voltage supply and a processus of simple manufacture and therefore V _{ OH } is limited to V _{ DD } - V _{ T }.

The linear enhancement load inverter is shown in fig. (b). It always operates in linear region; therefore the level V _{ OH } is equal to V _{ DD }.

The linear load inverter has a higher load noise margin compared to the saturated enhancement inverter.But, the downside of linear enhancement inverter is that it requires two separate power supplies and both circuits suffer from high power dissipation. 'extension are not used in large scale digital applications.

## NMOS exhaustion load

Disadvantages of charging inverter extension can be overcome using the depletion charge inverter. Compared to the improvementcharge inverter, depletion charge inverter need some additional manufacturing steps for the canal implant to adjust the threshold voltage of the load.

The advantages of the depletion charge inverter are: clean VTC transition, better noise margin, single power supply smaller overall layout area.

As shown in the figure, the gate and the source terminal of the load are connected; So, V _{ GS } = 0. Thus, the threshold voltage of the load is negative. Therefore,

$$ V_ {GS, load}> V_ {T, load} $$ is satisfied

Therefore, the charging device always has a conduction channel independently of the input and output voltage

When the load transistor is in the saturation region, the load current is given by

$$ I_ {D, load } = frac {K_ {n, load}} {2} left [-V_ {T, load} left (V_ {out} right) right] ^ {2} $$

Lhen the load transistor is in a linear region, the load current is given by

$$ I_ {D, load} = frac {K_ {n, load}} {2} left [2 left | V_ {T, load} left (V_ {output} right) right |. left (V_ {DD} -V_ {output} right) - left (V_ {DD} - V_ {out} right) ^ {2} right] $$

The voltage transfer characteristics of the Depletion load inverter are shown in the figure below -

## CMOS Inverter - Circuit, Operation and Deion

The circuit of CMOS inverter is shown in the figure. Here, nMOS and pMOS transistors work as transistors drivers; when one transistor is on, the other is off.

This configuration is called ** Complementary MOS (CMOS) **. The input is connected to the gate terminal of both transistors so that both can be driven directly with input voltages. The substrate of the nMOS is connected to ground and the substrat from pMOS is connected to the power supply, V _{ DD }.

So V _{ SB } = 0 for both transistors.

$$ V_ {GS, n} = V_ {in} $$

$$ V_ {DS, n} = V_ {out} $$

And,

$$ V_ {GS, p} = V_ {in} -V_ {DD} $$

$$ V_ {DS, p} = V_ {out} -V_ {DD} $$

When the input of nMOS is less than the threshold voltage (V _{ in } TO, n ), the nMOS is cut and the pMOS is in the linear region. Thus, the drain current of the two transistors is zero.

$$ I_ {D, n} = I_ {D, p} = 0 $$

Therefore, the output voltage V _{ OH } is equal to the supply voltage.

$$ V_ {out} = V_ {OH} = V_ {DD} $$

When the input voltage is greater than V _{ DD } + V _{ TO, p }, the pMOS transistor is in the cutoff region and the nMOS is in the regionlinear, therefore the drain current of the two transistors is zero.

$$ I_ {D, n} = I_ {D, p} = 0 $$

Therefore, the output voltage V _{ OL } is zero.

$$ V_ {out} = V_ {OL} = 0 $$

The nMOS is running in the saturation region if V _{ in }> V _{ TO } and if the following conditions are met.

$$ V_ {DS, n} geq V_ {GS, n} -V_ {TO, n} $$

$$ V_ {out} geq V_ {in} - V_ {TO, n} $$

The pMOS is running in the saturation region if V _{ in } DD + V _{ TO, p } and if following the wing conditions are met.

$$ V_ {DS, p} leq V_ {GS, p} -V_ {TO, p} $$

$$ V_ {out} leq V_ {in} - V_ {TO, p} $$

For different input voltage values, the regions of operation are listed below for both transistors.

Region | V _{ in } | V _{ out } | nMOS | pMOS |

A | TO, n | V _{ OH } | Cut - off | Linear |

B | V _{ IL } | High ≈ V _{ OH } | Saturation | Linear |

C | V _{ e } | V _{ e } | Saturation | Saturation |

D | V _{ IH } | Low ≈ V _{ OL } | Linear | Saturation |

E | > (V _{ DD } + V _{ TO, p }) | V _{ OL } | Linear | Cutout |

TheCMOS VTC is shown in the figure below -