VLSI Design  MOS Transistor
Complementary MOSFET (CMOS) technology is widely used today to form circuits in many and varied applications. Today's computers, processors and mobile phones use CMOS because of several key advantages. CMOS offers low power dissipation, relatively high speed, high noise margins in both states, and will operate over a wide range of source and input voltages (provided the source voltage is fixed). p>
For the processes we are going to discuss, the type of transistor available is the Metal Oxide Semiconductor Field Effect Transistor (MOSFET). These transistors are "sandwich " formed consisting of a semiconductor layer, usually a wafer, or wafer, from a single crystal of silicon; a layer of silicon dioxide (the oxide) and a layer of l.
Ststructure of a MOSFET
As the figure shows, the MOS structure contains three layers 
The MOS structure forms a capacitor, with the gate and the substrate as two plates and an oxide layer as the dielectric material. The thickness of the dielectric material (SiO _{ 2 } ) is typically between 10nm and 50nm. The concentration and distribution of carriers in the substrate can be manipulated by an external voltage applied to the gate and terminal of the substrate. Now to understand the structure of MOS, first consider the basic electrical properties of the Ptype semiconductor substrate.
The concentration of the support in the semiconductor material followsstill the law of mass action . The law of mass action is given by 
$$ np = n_ {i} ^ {2} $$
Where,

n is the concentration of carriers of elected rons

p is the concentration of hole carriers

n _{ i } is the intrinsic concentration of silicon support
Now suppose that the substrate is also doped with the acceptor (boron) concentration N _{ A }. So, the concentration of electrons and holes in the ptype substrate is
$$ n_ {po} = frac {n_ {i} ^ {2}} {N_ {A}} $ $
$$ p_ {po} = N_ {A} $$
Here, doping concentration N_{ A } is (10 ^{ 15 } to 10 ^{ 16 } cm ^{  3 }) greater than the intrinsic concentration ni. Now, to understand the MOS structure, considerthe energy level diagram of the ptype silicon substrate.
As shown in the figure, the band gap between the conduction band and the band valance is 1.1 eV. Here, the Fermi potential Φ _{ F } is the difference between the intrinsic Fermi level (E _{ i }) and Fermi level (E _{FP}).
Where Fermi level E _{ F } depends on the doping concentration. The Fermi potential Φ _{ F } is the difference between the intrinsic Fermi level (E _{ i }) and Fermi level (E _{ FP }).
Mathematically,
$$ Phi_ {Fp} = frac {E_ {F} E_ {i}} {q} $$
The potential difference between the conduction band and the free space is called electron affinity and is denoted qx.
Therefore, the energy required for an electron to pass from the level of Fermi to free space is called work function (qΦ _{ S }) and it is given by
$$ q Phi _ {s} = (E_ {c} E_ {F}) + qx $$
The following figure shows the energy band diagram of the components that make up the MOS.
As shown in the figure above, the SiO _{ 2 } insulating layer has a wide energy gap of 8 eV and the working function is 0.95 eV. The l gate has a working function of 4.1 eV. Here the working functions are different, so it will create a voltage drop in the MOS system. The figure below shows the combined energy band diagram of the MOS system.
As shown in this figure, the level closed potential of the l gate and of the semiconductor (Si) are at the same potential. The Fermi potential at the surface is called the surface potential Φ _{ S } and it is smaller than theFermi potential Φ _{ F } in magnitude.
How a MOSFET Works
The MOSFET consists of a MOS capacitor with two pn junctions placed close to the channel region and this region is voltage controlled grid. To make the pn junction reverse biased, the potential of the substrate is kept lower than the potential of the other three terminals.
If the gate voltage will be increased beyond the threshold voltage (V _{ GS }> V _{ TO }), an inversion layer will be established on the surface and an ntype channel will be formed between the source and the drain. This ntype channel will carry the drain current according to the value V _{ DS }.
For different value of V _{ DS }, MOSFET can be used in different regions as explained below.
Linear region
To V _{ DS }= 0, thermal equilibrium exists in the region of the reverse channel, and the drain current I _{ D } = 0. Now if the drain voltage is small, V _{ DS }> 0 is applied, a drain current proportional to V _{ DS } will start to flow from source to drain across the canal.
The channel gives a continuous path for the current flow from source to drain. This mode of operation is called a linear region . The sectional view of an nchannel MOSFET, operating in a linear region, is shown in the figure below.
At the edge of the saturation region
Now if the V _{ DS } is increased, the loads in the channel and the depth of the channel decrease at the end of the drain. For V _{ DS } = V _{ DSAT }, the charges in the channel are reduced to zero, which is called a pinch pointement . The crosssectional view of the nchannel MOSFET operating at the edge of the saturation region is shown in the figure below.
Saturation region
For V _{ DS }>V_{ DSAT }, a depleted surface forms near the drain, and by increasing the drain voltage, this depleted region expands to the source.
This mode of operation is called Saturation region . The electrons coming from the source towards the end of the channel, enter the depletion region of the drain and are accelerated towards the drain in a high electric field.
MOSFET current  Voltage characteristics
To understand the currentvoltage characteristic of MOSFET, the channel approximation is performed. Without this approximation, the threedimensional analysis of the MOS system becomes complex. Gradual Channel Approximation (GCA) for characterizationCurrentvoltage stic will reduce the analysis problem.
Gradual Channel Approximation (GCA)
Consider the sectional view of nchannel MOSFETs operating in linear mode. Here the source and the substrate are connected to the gr ound. V _{ S } = V _{ B } = 0. The door to the source (V _{ GS }) and drainsource voltage (V _{ DS }) are the external parameters that control the drain current I _{ D }.
The voltage, V _{ GS } is set to a voltage greater than the threshold voltage V _{ TO }, to create a channel between the source and the drain. As shown in the figure, the x direction is perpendicular to the surface and y direction is parallel to the surface.
Here, y = 0 at the source end as shown in the figure. The voltage of the channel, with respect to the source, is shownfelt by V_{C(Y)} . Suppose the threshold voltage VTO is constant along the channel region, between y = 0 and y = L. The boundary conditions for the channel voltage V _{ C } are 
$$ V_ {c} left (y = 0 right) = V_ {s} = 0, and, V_ {c} left (y = L right) = V_ {DS} $ $
We can also assume that
$$ V_ {GS} geq V_ {TO} $$ and
$$ V_ {GD} = V_ {GS} V_ {DS} geq V_ {TO} $$
Let Q1 (y) be the total charge d Mobile electrons in the surface inversion layer. This electronic charge can be expressed by 
$$ Q1 (y) =  C_ {ox}. [V_ {GS} V_ {C (Y)}  V_ {TO}] $$
The figure below shows the spatial geometry of the surface inversion layer and indicates its dimensions . The inversion layer shrinks as we move from the drain to the source. Now if we consider thesmall region dy of channel length L then the incremental resistance dR offered by this region can be expressed as 
$$ dR =  frac {dy} {w. mu _ {n} .Q1 (y)} $$
Here the minus sign is due to the negative polarity of the charge of the inversion layer Q1 and μ _{ n } is the bedded moving surface, which is constant. Now replace the value of Q1 (y) in the equation dR 
$$ dR =  frac {dy} {w. mu _ {n}. left {C_ {ox} left [V_ {GS} V_ {C left (Y right)} right] V_ {TO} right}} $$
$$ dR = frac {dy} {w. mu _ {n} .C_ {ox} left [V_ {GS} V_ {C left (Y right)} right] V_ {TO}} $$
The voltage drop in the small region of dy can be given by
$$ dV_ {c} = I_ {D} .dR $ $
Put the value of dR in the equation above
$$ dV_ {C} = I_ {D}. frac {dy} {w. mu_ {n} .C_ {ox} left [V_ {GS} V_ {C (Y)} right] V_ {TO}} $$
$$ w. mu _ {n}.C_ {ox} left [V_ {GS} V_ {C (Y)}  V_ {TO} right] .dV_ {C} = I_ {D} .dy $$
To get the 'ID of the drain current over the whole region of the channel, the above equation can be integrated along the channel from y = 0 to y = L and voltages V _{ C (y) } = 0 to V _{ C (y) } = V _{ DS },
$$ C_ {ox} .w. mu _ {n}. int_ {V_ {c} = 0} ^ {V_ {DS}} left [V_ {GS} V_ {C left (Y right)}  V_ {TO} right] .dV_ {C} = int_ {Y = 0 } ^ {L} I_ {D} .dy $$
$$ frac {C_ {ox} .w. mu _ {n}} {2} left (2 left [V_ {GS} V_ {TO} right] V_ {DS} V_ {DS} ^ {2} right) = I_ {D} left [L0 right] $$
$$ I_ {D} = frac {C_ {ox}. mu _ {n}} {2}. frac {w} {L} left (2 left [V_ {GS} V_ {TO} right] V_ {DS} V_ {DS} ^ {2} right) $$
For the region linear V _{ DS } GS  V _{ TO }. For the region of saturation, the value of V _{ DS } is greater than (V _{ GS }  V _{ TO }). Therefore, for the saturation region V _{ DS } = (V _{ GS }  V _{ TO }).
$$ I_ {D} = C_ {ox}. mu _ {n}. frac {w} {2} left (frac {left [2V_ {DS} right] V_ {DS} V_ {DS} ^ {2}} {L} right) $$
$$ I_ {D} = C_ {ox}. mu _ {n}. frac {w} {2} left (frac {2V_ {DS} ^ {2} V_ {DS} ^ {2}} {L} right) $$
$$ I_ {D} = C_ {ox}. mu _ {n}. frac {w} {2} left (frac {V_ {DS} ^ {2}} {L} right) $$
$$ I_ {D} = C_ {ox}. mu _ {n}. frac {w} {2} left (frac {left [V_ {GS} V_ {TO} right] ^ {2}} {L} right) $$